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www..com SIP42101 New Product Vishay Siliconix Half-Bridge N-Channel MOSFET Driver for Motor Control FEATURES D D D D D D D D 5-V Gate Drive Pb-free Undervoltage Lockout Available Internal Bootstrap Diode Adaptive Shoot-Through Protection Motor Braking Shutdown Control Matched Rising and Falling Propagation Delays Drive MOSFETs In 4.5- to 50-V Systems APPLICATIONS D H-Bridge Motor Controls D 3-Phase Motor Controls DESCRIPTION The SIP42101 is a high-speed half-bridge MOSFET driver with adaptive shoot-through protection for motor driving applications. The high-side driver is bootstrapped to allow driving n-channel MOSFETs. The Brake pin forces the lowside MOSFET on, providing a braking function in H-bridge and 3-phase topologies. The SIP42101 comes with adaptive shoot-through protection to prevent simultaneous conduction of the external MOSFETs. The SIP42101 is available in both standard and lead (Pb)-free 10-Pin MLP33 packages and is specified to operate over the industrial temperature range of -40 _C to 85 _C. FUNCTIONAL BLOCK DIAGRAM +5 to 50 V +5 V VDD BOOT OUTH SIP42101 SD Controller PWM BRAKE LX Motor Winding OUTL GND GND GND Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www.vishay.com 1 www..com SIP42101 Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V) VDD, PWM, SD, BRAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V LX, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 V BOOT to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa,b MLP-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 mW Thermal Impedance (QJA)a,b MLP-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105_C/W Notes a. Device mounted with all leads soldered or welded to PC board. a. Derate 9.6 mW/_C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V) VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 50 V CBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nF to 1 mF Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C SPECIFICATIONSa Test Conditions Unless Specified Parameter Power Supplies Supply Voltage Quiescent Current Shutdown Current VDD IDDQ ISD fPWM = 1 MHz, CLOAD = 0 4.5 2.2 5.5 3.0 1 V mA mA Limits Mina Typb Maxa Unit Symbol VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = -40 to 85_C Reference Voltage Break-Before-Make VBBM 1 V PWM Input Input High Input Low Bias Current VIH VIL IB VIH VIL Brake SD IB SD = 5 V 3.5 2.0 "0.3 4.0 VDD 0.5 "1 V mA SD, BRAKE Inputs Input High Input Low Bias Current VDD 1.0 "1 7 V mA High-Side Undervoltage Lockout Threshold VUVHS Rising or Falling 2.5 3.35 3.75 V Bootstrap Diode Forward Voltage VF IF = 10 mA, TA = 25_C 0.70 0.76 0.82 V MOSFET Drivers High-Side Drive Currentc Low-Side Drive Currentc High-Side High Side Driver Impedance Low-Side Low Side Driver Impedance IPKH(source) IPKH(sink) IPKL(source) IPKL(sink) RDH(source) RDH(sink) RDL(source) RDL(sink) 0.9 1.1 0.8 1.5 2.5 2.2 3.4 1.4 3.8 3.3 5.1 2.1 W A www.vishay.com 2 Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www..com SIP42101 New Product SPECIFICATIONSa Test Conditions Unless Specified Parameter MOSFET Drivers High-Side Rise Time High-Side Fall Time High-Side High Side Propagation Delayc Low-Side Rise Time Low-Side Fall Time Low-Side Low Side Propagation Delayc trH tfH td(off)H td(on)H trL tfL td(off)L td(on)L 10% - 90% 90% - 10% See Timing Waveforms See Timing Waveforms 10% - 90% 90% - 10% See Timing Waveforms See Timing Waveforms 32 36 20 30 45 20 30 30 55 30 ns 40 45 Vishay Siliconix Limits Mina Typb Maxa Unit Symbol VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = -40 to 85_C LX Timer LX Falling Timeoutc tLX 420 ns VDD Undervoltage Lockout Threshold Rising Threshold Falling Hysteresis Power on Reset Timec VUVLOR VUVLOF VH 3.7 4.35 4.1 0.4 2.5 ms 4.5 V Thermal Shutdown Temperature Hysteresis TSD TH Temperature Rising Temperature Falling 165 25 _C Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VDD = 5V unless otherwise noted. c. Guaranteed by design. TIMING WAVEFORMS PWM 50% 90% 10% tfH 90% OUTL td(off)H 10% 90% 10% td(on)H 10% trH 50% 90% OUTH trL td(off)L tfL td(on)L Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www.vishay.com 3 www..com SIP42101 Vishay Siliconix New Product PIN CONFIGURATION AND TRUTH TABLE MLP33 OUTH BOOT PWM SD GND 10 9 8 7 6 LX BRAKE NC VDD OUTL TRUTH TABLE PWM L H X X SD H H H L BRAKE L L H X OUTH L H L L OUTL H L H L 2 3 4 5 Top View ORDERING INFORMATION Standard Part Number SIP42101DM-T1 Lead(Pb)-Free Part Number SIP42101DM-T1--E3 Temperature Range -40 to 85_C Marking 42101 Eval Kit SIP42101DB Temperature Range -40 to 85_C PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 Name OUTH BOOT PWM SD GND OUTL VDD NC BRAKE LX High-side MOSFET gate drive Function Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX. Input signal for the MOSFET drivers Shuts down the driver Ground Synchronous or low-side MOSFET gate drive +5-V supply No Connect Forces OUTL high and OUTH low Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor www.vishay.com 4 Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www..com SIP42101 New Product FUNCTIONAL BLOCK DIAGRAM Vishay Siliconix VDD BOOT SD UVLO OTP OUTH LX PWM - + VBBM BRAKE VDD OUTL GND Figure 1. DETAILED OPERATION PWM The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. Low-Side Driver The supplies for the low-side driver are VDD and GND. During shutdown, OUTL is held low. High-Side Driver The high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel MOSFET can be used for the high-side switch. The supplies for the high-side driver are BOOT and LX. The voltage is supplied by a floating bootstrap capacitor, which is continually recharged by the switching action of the output. During shutdown OUTH is held low. Bootstrap Circuit The internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An Document Number: 73176 S-50265--Rev. B, 21-Feb-05 integrated bootstrap diode replaces the external Schottky diode needed for the bootstrap circuit; only a capacitor is necessary to complete the bootstrap circuit. The bootstrap capacitor is sized according to, CBOOT = (QGATE/DVBOOT - LX) x 10 where QGATE is the gate charge needed to turn on the high-side MOSFET and DVBOOT - LX is the amount of droop allowed in the bootstrapped supply voltage when the high-side MOSFET is driven high. The bootstrap capacitor value is typically 0.1 mF to 1 mF. The bootstrap capacitor voltage rating must be greater than VDD + 5 V to withstand transient spikes and ringing. Shoot-Through Protection The external MOSFETs are prevented from conducting at the same time during transitions. Break-before-make circuits monitor the voltages on the LX pin and the OUTL pin and control the switching as follows: When the signal on PWM goes low, OUTH will go low after an internal propagation delay. After the voltage on LX falls below 1 V by the inductor action, the low-side driver is enabled and OUTL goes high after some delay. When the signal on PWM goes high, OUTL will go low after an internal propagation delay. After the voltage on OUTL drops below 1 V the high-side driver is enabled and OUTH will go high after an internal propagation delay. If LX does not drop below 1 V within 400 ns after OUTH goes low, OUTL is forced high until the next PWM transition. www.vishay.com 5 www..com SIP42101 Vishay Siliconix New Product Matched Propagation Delays Rising and falling propagation delays are matched from PWM to LX to within 8 ns. Brake Input When BRAKE is high, OUTH is forced low and OUTL is forced high to create active braking of the motor. When this input is low, operation is normal. Shutdown The driver enters shutdown mode when SD is low. Shutdown current is less than 1 mA. VDD Bypass Capacitor MOSFET drivers draw large peak currents from the supplies when they switch. A local bypass capacitor is required to supply this current and reduce power supply noise. Connect a 1-mF ceramic capacitor as close as practical between the VDD and GND pins. Undervoltage Lockout Undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. The UVLO circuit forces OUTL and OUTH to low when VDD is below its specified voltage. A separate UVLO forces OUTH low when the voltage between BOOT and LX is below the specified voltage. Thermal Protection If the die temperature rises above 165_C, the thermal protection disables the drivers. The drivers are re-enabled after the die temperature has decreased below 140_C. TYPICAL CHARACTERISTICS 50 IDD vs. CLOAD vs. Frequency 40 IDD (mA) 30 1 MHz 20 200 kHz 10 500 kHz 0 0 1 2 3 4 5 CLOAD (nF) www.vishay.com 6 Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www..com SIP42101 New Product TYPICAL WAVEFORMS Figure 2. PWM Signal vs. LX (Rising) Figure 3. PWM Signal vs. LX (Falling) Vishay Siliconix PWM IN 2 V/div PWM IN 2 V/div VLX 2 V/div VLX 2 V/div 50 ns/div 50 ns/div Figure 4. PWM Signal vs. HS Gate and LS Gate (Rising) Figure 5. PWM Signal vs. HS Gate and LS Gate (Falling) PWM IN 5 V/div PWM IN 5 V/div HS Gate 5 V/div HS Gate 5 V/div LS Gate 5 V/div LS Gate 5 V/div 50 ns/div 50 ns/div Figure 6. Brake Enable VBRAKE 5 V/div HS Gate 5 V/div LS Gate 2 V/div 10 ms/div Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73176. Document Number: 73176 S-50265--Rev. B, 21-Feb-05 www.vishay.com 7 |
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